· Course Instructor 

- Provided expert HDL and HVL language and methodology training to hundreds of satisfied engineers and managers.

- Consistently received outstanding reviews and future course recommendations.

- Taught courses independently in the US, Canada, and Europe. 

- Published and presented at industry leading conferences in Germany and United States. 

- Delivered "in house" courses as well as courses for EDA vendors.

· Senior ASIC Methodology Consultant 

- Provided leadership to clients engineering teams, which meant advocating design reuse, creating and enforcing the Verification Plan, leading code reviews, and guiding EDA tool selection.

- Delivered best design techniques to Fortune 100 clients who needed point demand engineering, which involved the following:

· Successfully led verification team to recover schedule loses for industry common octal T1/E1 Framer. Delivered complete Verilog Behavioral Model, test suite, and verification infrastructure.

· Created complete ‘e’ functional coverage model to find coverage holes for the industry common C166xx microcontroller.  Exposed several design flaws prior to next release of the part.  Created an ‘e’ reference model to predict results of random instruction group injection through the core.  Excellent communication skills were needed on this multi-lingual team spanning three countries.

· Completed Vera ATM over UTOPIA model for EDA client design seminar.

· Intellectual Property Developer

- Lead designer on AAL5/ATM Verification Component (VC) IP implemented in ‘e’.

- Teamed with industry experts to create IP guidelines and standards. 

- Implemented use of standard library units common to each VC, ensuring consistent implementation and efficient reuse.

· Project Leader 

- Managed and led team on the verification task for a DSP ASIC for cellular application.

- Introduced revolutionary method for VHDL test harnessing not seen before in industry.

- Client requested return for guidance on two contract extensions.

· Complete IT Support for Remote Office Local Area Network (LAN)

- Determined the most efficient and secure connection on a per client basis.

- Solely responsible for all purchasing and networking of workstations.

- Managed remote Flex LM license server connections for local use in office and training sessions.

· Course instructor.  Prepared and taught “Introduction to VHDL and ASIC Design” on a bi-monthly basis.

· ASIC/FPGA designer Worked in a technology group that provided ASIC design expertise to all product groups. Wrote VHDL testbenches and synthesizable module code for various designs; BLINK 1Gbit bus interface, EKV DSP modem chipset, 777 flight display driver, FIR filters and GPS L-band receiver control. Mentored new engineers on team. Pioneered telecommuting pilot program.

· Hardware designer  MDM 3001 HF modem PCB design using 80186 CPU and ADSP-21062 DSP.

· Hardware designer  VP-115 Narrow Band Secure Voice Equipment PCB design and test.  Involved 80186 CPU and TMS320C50 DSP.  Designed Visual C++ automated test routines.

· Hardware designer  Antenna Coupler design responsibilities included control and power supply.

· Electrical Engineer Analog and digital CMOS circuit design for Flash EPROM's.  Responsible for design, SPICE analysis, and layout of memory circuits.

· Electrical Engineer co-op (3 terms)

- Software engineering for the Electronic Flight Display used on the Canadair Regional Jet.  Created the Ada software to process the ARINC 429 data.

- Design for the Miniature Sensor Unit used on the Tomahawk Land Attack Missile. 

- Modified the Control Display Unit used on the AH-64 Apache helicopter for the US army.